1. Field of the Invention
The present invention relates to a semiconductor memory and, in particular, it relates to a semiconductor memory provided with a plurality of banks.
2. Description of the Related Art
The use of DRAM provided with a plurality of banks (hereafter referred to as "multibank DRAM") as semiconductor memory that enables high speed access to memory cells has become increasingly common in recent years. Normally, in a multibank DRAM, a bank selected by a word line (hereafter referred to as a "row-active bank") and a bank selected by a column line (hereafter referred to as a "column-active bank") do not correspond with each other on a one-to-one basis. Namely, in a multibank DRAM in which the column line is shared by a plurality of banks, one bank is selected to function as a row-active bank by a word line and all the banks including the aforementioned one bank are selected by the column line 1o function as column-active banks.
In a multibank DRAM, the equalization of a given bit line pair is canceled by setting one word line from the logically low level (hereafter referred to as the "L level") to the logically high level (hereafter referred to as the "H level") concurrently with other word lines that are set from the L level to the H level. By canceling the equalization in this manner, the data stored in the memory cell corresponding to the one bit line pair are read out to the one bit line pair, and the data thus read out are amplified by a sense amplifier to source potentials VDD and VSS. However, since the equalization of the sub-data bus connected to the one bit line pair via a column switch is not yet cleared at this point, the data that have been amplified by the sense amplifier are held at the one bit line pair instead of being transferred to the sub-data bus.
Since the data that have been read out from the memory cells are amplified to the source potentials VDD and VSS and are held at the one bit line pair, a through current is generated between the one bit line pair and the sub-data bus which corresponds to the bit line pair, by the difference between the source potential VDD and the potential 1/2 VDD and the difference between the potential 1/2 VDD and the source potential VSS.
In order to solve this problem, the generation of a through current is prevented in a multibank DRAM in the prior art by providing a column decoder and a column line for each bank. However, this solution achieved by providing many column decoders results in an undesirably large circuit scale.
It is possible to prevent the generation of a through current by providing a common column decoder and a common column line to serve a plurality of banks and canceling the equalization of the sub-data bus at a row-active bank that does not match the column-active bank. However, since the data that are stored in the memory cells at non column-active banks are transferred to the sub-data bus, a problem of an increase in the power consumption results from this transfer operation.